Building the future of WiGig/60GHz

Tensorcom is a leading provider of ultra-low power WiGig/60GHz technologies for markets as diverse as 60GHz solutions to wireless medical applications such as secure, wireless, Personal Medical Information Cards. If you are an individual who has high energy, are a critical thinker, are passionate about what you do and would like to apply for any of our open positions, please contact us (career@tensorcom.com). Thank you in advance for your consideration and we look forward to talking with you soon.

Our Current Job Openings

 ASIC Design Engineer

Tensorcom, a pioneer in developing innovative semiconductors for high-speed millimeter wave, ultra- low power, wireless communication chipsets, is looking for a candidate who is interested in working on complex, low power, ASIC designs for our next generation WiGig/IEEE 802.11ad compliant SoCs. The interested candidate will participate in a range of ASIC development activities such as defining the SoC architecture, the development of RTL code, the taping-out of the chip, and the evaluation of chip performance.

In addition to excellent technical skills, good English communication skills are required.

 

Responsibilities

The interested candidate will be responsible for:
 

• Defining the architecture and micro-architecture of WiGig/802.11ad MAC digital subsystems
• SoC development and integration
• RTL design using Verilog/System Verilog
• Testbench and test cases development
• ASIC emulation on an FPGA platform
• Collaborating with the software and physical design teams to resolve any issues during the development process
• Paying attention to design and implementation details, and documentation

 

 Qua li fica tions:

The interested candidate shall have demonstrable experience in:

• ASIC flow activities such as:
  • Using front-end ASIC tools to perform simulations, lint/CDC, synthesis, formal verification, static timing, and power analysis
  • Using Verilog and/or System Verilog proficiently
• Processor Subsystem:
  • Understanding of ARM/RISC-V processor, memory, bus fabric, and interface IPs

• Hardware/Software interfacing
• Processor subsystems bring up

• Verification activities such as:
  • Developing a testbench and test cases
  • Emulating an ASIC on an FPGA development platform

• SoC system architecture and common peripheral interfaces such as SPI, I2C, UART, GPIO, and JTAG

Previous working experience on WLAN SoCs, Ethernet NICs, or Storage SoCs is desirable.
 

 EDUCATION / MAJOR

• BS     ■ MS       ■ PhD

Electrical or Computer Engineering, Communications Engineering, or similar applicable technical degrees.
 

 E X P E RIE NCE

5+ years



 

 Modem Design Engineer

Tensorcom, a pioneer in developing innovative semiconductors for high-speed millimeter wave, ultra- low power, wireless communication chipsets, is looking for a candidate who is interested in working on complex ASIC designs for our next generation 60GHz, IEEE 802.11ad/WiGig compliant SoCs with specific emphasis on developing RTL code for the digital baseband module. The candidate will participate in a range of ASIC development activities such as defining the digital modem architecture, the evaluation of competing efficient, compact signal processing algorithms, the development of RTL code, the taping-out of the chip, and the evaluation of the chip’s performance.

In addition to excellent technical skills, good English communication skills are required.
 

Responsibilities

The interested candidate will be responsible for:
 

• • Defining the micro-architecture of IEEE 802.11ad compliant Wireless Modem’s Digital Signal Processing (DSP) blocks.
• Developing and verifying the Register-Transfer-Level (RTL) code using Verilog / System Verilog
• Performing block level verification against a cycle-accurate, finite precision, behavioral model
• Performing block level static timing and power estimation/analysis/optimization
• Evaluating the digital modem’s performance using an FPGA platform
• Creating detailed documentation.

 

 Quali fica tions:

The interested candidate shall have demonstrable experience and/or knowledge in:

• ASIC flow activities such as:
  • Using front-end ASIC tools to perform simulations, CDC, synthesis, static timing, and power analysis
  • Using Verilog and/or System Verilog proficiently
• Modem development activities such as:
  • Implementing DSP blocks such as digital filters, time or frequency domain equalizers, channel encoder/decoders and/or signal acquisition
  • Understanding the general concepts of communications and information theory
  • Being familiar with general forms of signal impairments within a wireless channel
• Verification activities such as:
  • Developing a test bench and test cases
  • Emulating an ASIC on an FPGA development platform

• SoC system architecture and common interfaces

Previous work experience with high-speed Wireless Modems is desirable
 

 EDUCATION / MAJOR

• BS    ■ MS

Electrical or Computer Engineering, Communications Engineering, or similar applicable technical

degrees.
 

 E X P E RIE NCE

5+ years
 

 IC Layout Engineer

Tensorcom, a pioneer in developing innovative semiconductors for high-speed millimeter wave, ultra- low power, wireless communication chipsets, is looking for a candidate who is interested in analog circuit layout for our next generation 60GHz, IEEE 802.11ad/ay compliant SoCs.

In addition to excellent technical skills, good English communication skills are required.
 

Responsibilities

The interested candidate will be responsible for:

• • Setting up the LVS, DRC, ERC environments and debugging verification issues using the Cadence tool suite
  • Collaborating with an interdisciplinary functional team to define and develop the design flow, optimization of the silicon floor plan, and bump and package pinouts.
  • Setting up design rules and implementing in-house packaging layout to meet product requirements.
  • Optimizing package design to maintain signal and power integrity
  • Paying attention to lay out details and providing documentation

 

 Qua li fica tions:

The interested candidate shall have demonstrable experience and/or knowledge in:

• • The proficient use of the IC5 & 6.x Cadence Virtuoso tool suite
  • Layout techniques for device matching, parasitic minimization, RF shielding, and high frequency routing
  • The fundamentals of RC delay, EMI, and Crosstalk
  • IC packaging structures, chip-packaging, and package-board interactions.
  • The details of the semiconductor process and device physics
  • Laying out high speed I/O interfaces such as PCIe3.x, USB3.x, and GigE.

 

 EDUCATIO N / MAJOR

• BS /  ■ MS

Electrical or Computer Engineering, Communications Engineering, or similar applicable technical degrees.
 

 E X P E RIE NCE

5+ / 3+ years

 H/W Design Engineer

Tensorcom, a pioneer in developing