國立中興大學電機資訊學院 ( College of Electrical Engineering and Computer Science,NCHU )

電資學院副院長

王行健(Sying-Jyan Wang)

姓名

王行健(Sying-Jyan Wang)
職稱

專任教授兼電機資訊學院副院長
學歷

美國普林斯頓大學電機博士
電話

886-4-22840497-910
信箱

sjwang@cs.nchu.edu.tw
實驗室

VLSI/CAD實驗室
研究領域

VLSI Design, Digital Testing, CAD

重要經歷

Vice Dean, College of Electrical Engineering and Computer Science, National Chung Hsing University

2018~迄今

Professor, Institute of Computer Science, National Chung Hsing University

1999~迄今

Associate Professor, National Chung-Hsing University

1992~1999

Consultant, Bell Laboratories (Holmdel, NJ)

1989~1990

期刊論文

K. S.-M. Li, L. L.-Y. Chen, K. C.-C. Cheng, P. Y.-Y. Liao, S.-J. Wang, A. Y.-A. Huang, L. Chou, N. C.-Y. Tsai, and C.-S. Lee, “TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning,” IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 35, issue 2, pp. 372-374, May, 2022.

K. C.-C. Cheng, L. L.-Y. Chen, J.-W. Li, K. S.-M. Li, N. C.-Y. Tsai, S.-J. Wang, A. Y.-A. Huang, L. Chou, C.-S. Lee, J. E Chen, H.-C. Liang, and C.-L. Hsu, “Machine Learning Based Detection Method for Wafer Test Induced Defects, ” IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 34, issue 2, pp. 161-167, May, 2021.

K. S.-M. Li, P. Y.-Y. Liao, K. C.-C. Cheng, L. L.-Y. Chen, S.-J. Wang, A. Y.-A. Huang, L. Chou, G. C.-H. Han,J.-E Chen, H.-C. Liang, and C.-L. Hsu, “Hidden Wafer Scratch Defects Projection for Diagnosis and Quality Enhancement,” IEEE Transactions on Semiconductor Manufacturing, Vol. 34, issue 1, pp. 9-16, Feb. 2021.

K. S.-M. Li, N. C.-Y. Tsai, K. C.-C. Cheng, X.-H. Jiang, P. Y.-Y. Liao, S.-J. Wang, A. Y.-A Huang, L. Chou and C.-S. Lee, “TestDNA: Novel Wafer Defect Signature for Diagnosis and Pattern Recognition, ” IEEE Transactions on Semiconductor Manufacturing, Vol. 33, Issue 3, pp. 383-390, Aug. 2020.

S.-J. Wang, K.-T. Yeh, and K. S.-M. Li, “Exploiting distribution of unknown values in test responses to optimize test output compactors,” Integration, the VLSI Journal, Vol. 65, pp. 389-394, Mar. 2019. (SCI)

J.-D. Li, C.-H. kuo, G.-R. Lu, S.-J. Wang, K. S.-M. Li, T.-Y. Ho, H.-M. Chen, and S. Hu, “Co-placement optimization in sensor-reusable cyber-physical digitalmicrofluidic biochips,” Microelectronics Journal, Vol. 83, pp. 185-196, Jan. 2019. (SCI)

N.-C. Lai and S.-J. Wang, “Delay Test with Embedded Test Pattern Generator,” Journal of Information Science and Engineering (JISE), Vol. 29, No. 3, pp. 545-556, May. 2013. (SCI)

T.-H. Yeh and S.-J. Wang, ′Power-Aware High-Level Synthesis with Clock Skew Management,′ IEEE Transaction on Very Large Scale Integration Systems (TVLSI), Vol. 20, No. 1, pp. 167-171, 2012. (SCI)

S.-J. Wang and T.-H. Yeh, “High Level Test Synthesis with Hierarchical Test Generation for Delay Fault Testability,” IEEE Trans. on Computer-Aided Design, Vol. 28, No. 10, pp. 1583-1596, Oct. 2009. (SCI)

S.-J. Wang, K. S.-M. Li, S.-C. Chen, H.-Y. Shiu, and Y.-L. Chu, “Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power under Routing Constraint,” IEEE Trans. on Computer-Aided Design, Vol. 28, No. 5, pp. 716-727, May 2009. (SCI)

S.-J. Wang, P.-C. Tsai, H.-M. Weng, and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” Int’l J. Electrical Engineer, Special Issue of VLSI/CAD, Vol. 15, No. 2, pp. 71-78, Apr. 2008. (EI)

S.-J. Wang, K.-L. Peng, K.-C. Hsiao, and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Launch-off-Shift Transition Test Coverage,” ACM Trans. Design Automation of Electronic Systems, Vol. 13, No. 4, Sep. 2008. (SCI)

B.-J. Tsai and S.-J. Wang, “Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction,” IET Computer & Digital Techniques, Vol. 2, No. 6, pp. 434–444, 2008. (SCI)

B.-J. Tsai, S.-J. Wang, C.-H. Lin, and T.-H. Yeh, “Test data compression for minimum test application time,” Journal of Information Science and Engineering, Vol. 23, No. 6, pp. 1901-1909, Nov. 2007. (SCI)

N.-C. Lai and S.-J. Wang, “Low power BIST with smoother and scan-chain reorder under optimal cluster size,” IEEE Trans. on Computer-Aided Design, Vol. 25, No. 11, pp.2586-2594, Nov. 2006. (SCI)

M.-C. Wen, S.-J. Wang, and Y.-N. Lin, “Low-power parallel multiplier with column bypassing,” Electronic Letters, Vol. 41, No. 10, pp. 581-583, 2005. (SCI)

S.-J. Wang, “Distributed diagnosis in multistage interconnection networks,” Journal of Parallel and Distributed Computing, Vol. 61, No. 2, pp. 254-264, Feb. 2001. (SCI)

S.-J. Wang and C.-C. Lien, “Testability improvement by branch point control for conditional statements with multiple branches,” Journal of Information Science and Engineering, Vol. 16, No. 5, pp. 719-731, 2000. (SCI)

S.-J. Wang, “Test and diagnosis of faulty logic blocks in FPGAs,” IEE Proceedings Computers and Digital Techniques, Vol. 146, No. 2, pp. 100-106, 1999. (SCI)

S.-J. Wang, “Distributed routing in a fault-tolerant multistage interconnection network,” Information Processing Letters, Vol. 63, pp. 205-210, 1997. (SCI)

S.-J. Wang and M.D. Horng, “State assignment of finite state machines for low power applications,” Electronics Letters, Vol. 32, No. 25, pp. 2323-2324, 1996. (SCI)

S.-J. Wang, “Load-balancing in multistage interconnection networks under multiple-pass routing,” Journal of Parallel and Distributed Computing, Vol. 36, pp. 189-194, 1996. (SCI)

S.-J. Wang and N.K. Jha, “Correction to ‘Algorithm-based fault-tolerance for FFT networks’,” IEEE Trans. Computers, Vol. 43, No.10, pp. 1248, 1995. (SCI)

S.-J. Wang and N. K. Jha, “Algorithm-based fault-tolerance for FFT networks,” IEEE Trans. Computers, Vol. 43, No. 7, pp. 849-854, 1994. (SCI)

N. K. Jha and S.-J. Wang, “Design and synthesis of self-checking VLSI circuits,” IEEE Trans. CAD, Vol. 12, No. 6, pp. 878-887, 1993. (SCI)

V. P. Kumar and S.-J. Wang, “Reliability enhancement by time and space in multistage interconnection networks,” IEEE Transactions on Reliability, Vol. 40, No. 4, pp. 461-473, 1991. (SCI)

S.-J. Wang and N. K. Jha, “Systematic t-error correcting/all unidirectional error detecting codes with easy encoding/decoding,” International Journal of Computers and Mathematics with Applications, Vol. 20, No. 1, pp. 5-15, 1990. (SCI)

研討會論文

N. Sinhabahu, K. S.-M. Li, J. R. Wang, J.-D. Li, and S.-J. Wang, “Yield-Enhanced Probing Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test,” accepted by IEEE International Test Conference (ITC), June, 2022.

K. C.-C. Cheng, K. S.-M. Li, S.-J. Wang, A. Y.-A. Huang, C.-S. Lee, L. L.-Y. Chen, P. Y.-Y. Liao, and N. C.-Y. Tsai, “Wafer Defect Pattern Classification with Explainable Rule Based Decision Tree Methodology,” accepted by IEEE International Test Conference (ITC), June, 2022.

L. L.-Y. Chen, K. S.-M. Li, S.-J. Wang, A. Y.-A. Huang, C.-S. Lee, K. C.-C. Cheng, P. Y.-Y. Liao, and L. Chou, “Compositive Framework for Wafer Pattern Recognition with Confidence Relabeling Technique,” accepted by IEEE International Test Conference (ITC), June, 2022.

N. Sinhabahu, J.-D. Li, K. S.-M. Li, S.-J. Wang, and T.-Y. Ho, “Trojan Insertions of Fully Programmable Valve Arrays,” accepted by IEEE European Test Symposium (ETS), Feb. 2022.

J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Sep. 2021.

K. S.-M. Li, L. L.-Y. Chen, P. Y.-Y. Liao, S.-J. Wang, A. Y.-A. Huang, and K. C.-C. Cheng, “Integrated Scratch Marker for Wafer Defect Diagnosis,” in Proc. IEEE International Test Conference in Asia (ITC-Asia), July, 2021.

L. L.-Y. Chen, K. S.-M. Li, X.-H. Jiang, S.-J. Wang, A. Y.-A. Huang, J. E. Chen, H.-C. Liang, and C.-L. Hsu, “Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling,” in Proc. IEEE International Test Conference (ITC), July, 2021.

P. Y.-Y. Liao, K. S.-M. Li, L. L.-Y. Chen, S.-J. Wang, A. Y.-A. Huang, K. C.-C. Cheng, C.-Y. Tsai, and L. Chou, “WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques,” in Proc. IEEE International Test Conference (ITC), July, 2021.

S.-J. Wang, T.-H. Chang, and K. S.-M. Li, “Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2021.

K. S.-M. Li, L. L.-Y. Chen, P. Y.-Y. L., K. C.-C. Cheng, S.-J. Wang, A. Y.-A. Huang, L. Chou, N. C.-Y. Tsai, C.-S. Lee, G. C.-H. Han, J. E Chen, H.-C. Liang, and C.-L. Hsu, “Automatic Inspection for Wafer Defect Detection with Unsupervised Clustering Techniques,” in Proc. IEEE European Test Symposium (ETS), Feb. 2021.

F.-C. Wu, J.-D. Li, K. S.-M. Li, S.-J. Wang, and T.-Y. Ho, “Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Feb. 2021.

J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Enhanced Watermarking Scheme for Paper-Based Digital Microfluidic Biochip,” in Proc. 14th VLSI Test Technology Workshop, July 2020.

L. L.-Y. Chen, J.-D. Li, K. C.-C. Cheng, C.-Y. Tsai, P. Y.-Y. Liao, K. S.-M. Li, S.-J. Wang, L. Chou, C.-S. Lee, and A. Y.-A. Huang, “Wafer Defect Signature for Pattern Recognition by Ensemble Learning,” in Proc. 14th VLSI Test Technology Workshop, July 2020.

K. C.-C. Cheng, J.-D. Li, J.-W. Li, L. L.-Y. Chen, C.-Y. Tsai, P. Y.-Y. Liao, K. S.-M. Li, S.-J. Wang, L. Chou, C.-S. Lee, and A. Y.-A. Huang, “Site Dependence Detection with Artificial Intelligence in Wafer Test,” in Proc. 14th VLSI Test Technology Workshop, July 2020.

P. Y.-Y. Liao, J.-D. Li, K. S.-M. Li, L. Chou, K. C.-C. Cheng, A. Y.-A. Huang, and S.-J. Wang, “Wafermap Scratch Pattern Recognition with Machine Learning Techniques,” in Proc. 14th VLSI Test Technology Workshop, July 2020.

S.-J. Wang, C.-X. Tsai, Y.-W. Tseng, and K. S.-M. Li, “Feature Selection for Malicious Traffic Detection with Machine Learning,” in Proc. International Computer Symposium (ICS), Dec. 2020.

L. L.-Y. Chen, K. S.-M. Li, K. C.-C. Cheng, S.-J. Wang, A. Y.-A. Huang, N. C.-Y. Tsai, L. Chou, and C.-S. Lee, “TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning,” in Proc. IEEE International Test Conference (ITC), Nov. 2020.

J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Watermarking for Paper-Based Digital Microfluidic Biochips,” in Proc. IEEE International Test Conference in Asia (ITC-Asia), Sep. 2020.

K. S.-M. Li, P. Y.-Y. Liao, L. Chou, K. C.-C. Chen, A. Y.-A. Huang, S.-J. Wang, and G. C.-H Han, “PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques,” in Proc. IEEE European Test Symposium (ETS), May, 2020.

D.-C. Hu, H. Hashimoto, L.-F. Tseng, K. C.-C. Cheng, K. S.-M. Li, S.-J. Wang, S. Y.-S. Chen, J.E. Chen, C. Y.-H. Liu, and A. Y.-A. Huang, ′Innovative Practice on Wafer Test Innovations,′ in Proc. IEEE VLSI Test Symposium (VTS), Apr. 2020.

L.-F. Tseng, Ken C.-C. Cheng, J.-D. Li, K. S.-M. Li, and S.-J. Wang, ′Test System Parametric Yield Prediction Using Machine Learning Techniques,′ in Proc. IEEE VLSI Test Symposium (VTS), Apr. 2020.

K. C.-C. Cheng, K. S.-M. Li, A. Y.-A. Huang, J.-W. Li, L. L.-Y. Cheng, N. C.-Y. Tsai, S.-J. Wang, C.-S. Lee, Leon Chou, P. Y.-Y Liao, H.-C. Liang, and Jwu E Chen, “Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Mar. 2020.

A. Y.-A. Huang, K. S.-M. Li, S.-J. Wang, C.-Y. Tsai, K. C.-C. Cheng, X.-H. Jiang, L. Chou, and C.-S. Lee, “TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning,” in Proc. IEEE International Test Conference (ITC), Nov. 2019.

K. S.-M. Li, K. C.-C. Cheng, A. Y.-A. Huang, C.-Y. Tsai, S.-J. Wang, P. Y.-Y. Liao, L. Chou, and C.-S. Lee, ′Wafer Defect Diagnosis with Test Big Data Driven Techniques′, in Proc. Semiconductor Wafer Test Asia (SWTest Asia), Oct. 2019.

S.-J. Wang, Y.-S. Chen and K. S.-M. Li, “Adversarial Attack against Modeling Attack on PUFs,” accepted by Design Automation Conference (DAC) 2019.

J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Digital Rights Management for Paper-Based Microfluidic Biochips,” in Proc. IEEE 27th Asian Test Symposium, 2018, accepted.

J.-L. Wu, K. S.-M. Li, J.-D. Li, S.-J. Wang and T.-Y. Ho, “SOLAR: Skew-Consideration and Optimization of Control-Layer Pins Placement and Channel Routing in Reliable Flow-Based Microfluidic Biochips,” in Proc. 12th VLSI Test Technology Workshop, July 2018.

J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Design-for-Reliability for Paper-Based Digital Microfluidic Biochips,” in Proc. 12th VLSI Test Technology Workshop, July 2018.

S.-J. Wang, C.-H. Lien, Y.-Y. Li and K. S.-M. Li, “Scan PUF with On-Line Evaluation,” in Proc. 12th VLSI Test Technology Workshop, July 2018.

J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Design-for-testability for paper-based digital microfluidic biochips,” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Oct. 2017.

S.-J. Wang, J.-Y Wei, and K. S.-M. Li, “Detection for Stealthy Combinational Hardware Trojans,” in Proc. 11th VLSI Test Technology Workshop, July 2017.

J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Co-Placement Optimization of Cyber-Physical Digital Microfluidic Biochips for Testing,” in Proc. 11th VLSI Test Technology Workshop, July 2017.

S.-J. Wang, H.-H. Chen, C.-H. Lien and K. S.-M. Li, “Testing Clock Distribution Networks,” in Proc. 11th VLSI Test Technology Workshop, July 2017.

S.-J. Wang, J.-Y. Wei, S.-H. Huang and K. S.-M. Li, “Test Generation for Combinational Hardware Trojans,” in Proc. 10th VLSI Test Technology Workshop, July 2016.

J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “A Diagnosis Method with Fault Tolerance for Paper-Based Microfluidic Biochips,” in Proc. 27th VLSI Design/CAD Symposium, 2016.

J.-L. Wu, T.-Y Ho, K. S.-M. Li and S.-J. Wang, “Flow-based microfluidic synthesis con Considering Skew,” in Proc. 27th VLSI Design/CAD Symposium, 2016.

J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Conductive Wire Routing for Pin-Constrained Paper-Based Microfluidic Biochips,” in Proc. 27th VLSI Design/CAD Symposium, 2016.

S.-J. Wang, J.-Y. Wei, S.-H. Huang and K. S.-M. Li, “Test Generation for Combinational Hardware Trojans,” in Proc. 10th VLSI Test Technology Workshop, July 2016.

J.-D. Li, S.-J. Wang, K.S.-M. Li and T.-Y. Ho, “Test and Diagnosis of Paper-Based Microfluidic Biochips,” in Proc. 34th IEEE VLSI Test Symposium, pp.1-6, 2016.

J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, ′Congestion-and Timing-Driven Droplet Routing for Pin-Constrained Paper-Based Microfluidic Biochips ,′ in Pro. Proc. IEEE Asia Pacific Conference on Circuits and Systems, 2016.

S.-J. Wang, C.-H Lin and K. S.-M. Li, ′Synthesis of 3D Clock Tree with Pre-bond Testability ,′ in Proc. IEEE International Symposium on Circuits and Systems pp. 2654-2657, May 2013.

S.-J. Wang, Y.-S. Chen and K. S.-M. Li, ′Low-Cost Testing of TSVs in 3D Stacks with Pre-bond Testable Dies ,′ in Proc. IEEE International Symposium on VLSIDesign, Automation & Test, pp. 366-369, April 2013.

Y. Ho, K. S.-M. Li, S.-J. Wang, ′A 0.3 V Low-power Temperature-insensitive Ring Oscillator in 90 nm CMOS Process ,′ accept by IEEE International Symposiumon VLSI Design, Automation & Test, April, 2013.

R.-T., Gu, C.-Y., Ho, K. S.-M. Li, Y.-C. Ho, L.-B. Chen, K.-Y. Hsieh, J.-J Huang, B.-C. Cheng, S.-J. Wang and Z.-H. Gao, ′A Layout-Aware Test Methodology for Silicon Interposer in 3D System-in-a-Package ,′ in Proc. IEEE International Symposium on Next-Generation Electronics, pp. 41-44, February 2013.

B.-C. Cheng , K. S.-M. Li and S.-J Wang, ′De Bruijn Graph-Based Communication Modeling for Fault Tolerance in Smart Grids ,′ accept in Proc. IEEE Asia Pacific Conference on Circuits and Systems , pp. 623-626, December 2012.

S.-J Wang, H.-H. Hsu and K. S.-M. Li, ′Low-Power Delay Test Architecture for Pre-Bond Test ,′ accept in Proc. The IEEE International Symposium on Circuits and Systems , pp. 2321-2324, May 2012.

T.-H. Yeh, S.-J. Wang, and K. S.-M. Li, ′Interconnect Test for Core-based Designs with Known Circuit Characteristics and Test Patterns ,′ accept in Proc. IC Design & Technology (ICICDT) , 2012.

T.-H. Yeh and S.-J Wang, ′Thermal Safe High Level Test Synthesis for Hierarchical Testability,′ in Proc. Asain Test Symp., Dec., 2010.

T.-H. Tzeng and S.-J. Wang, “Fast and Accurate Statistical Static Timing Analysis,” in Proc. VLSI/CAD Symp., Hualian, Aug. 2009.

C.-C. Wang, J.-W. Liu, R.-C. Kuo, K. S.-M. Li, and S.-J. Wang, “A 1.8 V to 3.3 V Level-Converting Flip-Flop Design for Multiple Power Supply Systems,” in Proc. Int’l Symp. Integrated Circuits, Singapore, Dec. 2009.

S.-J. Wang, K.-L. Fu, and K. S.-M. Li, “Low Peak Power ATPG and Test Compactionfor n-Detection Test,” in Proc. Int’l Symp. on Circuit and System, June 2009.

K. S.-M. Li, M.-H. Hsieh, and S.-J. Wang, “Level Converting Scan Flip-Flops,” in Proc. Int’l Symp. on Circuit and System, June 2009.

S.-J. Wang, S.-J. Huang, and K. S.-M. Li, “Static and Dynamic Test Power Reduction in Scan-Based Testing,” in Proc. Int’l Symp. on VLSI Design, Automation, and Test, Apr. 2009.

N.-C. Lai and S.-J. Wang, “On-Chip Test Generation Mechanism for Scan-Based Two-Pattern Tests,” in Proc. Asian Test Symp., Sapporo, Japan, pp. 251-256, Nov. 2008.

S.-J. Wang, S.-C. Chen, and K. S.-M. Li, “Design and Analysis of Skewed-Distribution Scan Chain Partition for Improved Test Data Compression,” in Proc. Int’l Symp. on Circuit and System, Seattle, USA, pp. 2641-2644, May 2008.

S.-J. Wang, P.-C. Tsai, H.-M. Weng, and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” in Proc. Asian Test Symp., pp. 95-98, Oct. 2007.

S.-J. Wang, X.-L. Li, and K. S.-M. Li, “Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis,” in Proc. Asian Test Symp., pp. 129-132, Oct. 2007.

N.-C. Lai and S.-J. Wang, “Low-Capture-Power Test Generation by Specifying Minimum Set of Controlling Inputs,” in Proc. Asian Test Symp., pp. 413-418, Oct. 2007.

S.-J. Wang, Y.T. Chen, and K. S.-M. Li, “Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don’t-Care Filling,” in Proc. Int’l Symp. on Circuit and System, New Orleans, USA, pp. 27-30, May 2007.

S.-J. Wang and T.-H. Yeh, “High-Level Test Synthesis for Delay Fault Testability,” in Proc. Design, Automation, and Test in Europe, Nice, France, 2007.

B.-J. Tsai and S.-J. Wang, “Multi-Mode Segmented Scan Architecture with Layout-Aware Scan Chain Routing for Test Data and Test Time Reduction,” in Proc. Asian Test Symp., Fukuoka, Japan, pp. 225-230, Nov. 2006.

S.-J. Wang, K.-L. Peng, and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage,” in Proc. Asian Test Symp., Fukuoka, Japan, pp. 169-174, Nov. 2006.

T.-H. Yeh and S.-J. Wang, “Simultaneously Reducing Average Power and Peak Power in Behavioral Synthesis with Effective Shared Operations,” in Proc. VLSI/CAD Symp., Aug. 2005.

F.-M. Chang and S.-J. Wang, “Interconnect-Aware High-Level Synthesis and Floorplaning,” in Proc. VLSI/CAD Symp., Aug. 2005.

Y.-H. Fu and S.-J. Wang, “Test Data Compression with Partial LFSR-Reseeding,” in Proc. Asian Test Symp., Kolkata, India, Dec. 2005.

M.-C. Wen; S.-J. Wang, and Y.-N. Lin, “Low Power Parallel Multiplier with Column Bypassing,” in Proc. IEEE Int’l Symp. on Circuits and Systems, Vol. 2, pp. 1638-1641, Kobe, Japan, 2005.

P.-C. Tsai, S.-J. Wang, and F.-M. Chang, “FSM-Based Programmable Memory BIST with Macro Command,” in Proc. IEEE Int’l Workshop on Memory Technology, Design, and Testing (MTDT), pp. 72-77, Taipei, Taiwan, 2005.

P.-C. Tsai and S.-J. Wang, “Test Data Compression for Minimum Test Application Time,” in Proc. VLSI/CAD Symp., Aug. 2004.

Y.-H. Fu and S.-J. Wang, “Test Data Compression with LFSR-Reseeding and Seed Overlapping,” in Proc. VLSI/CAD Symp., Aug. 2004.

N.-C. Lai and S.-J. Wang, “Low Power BIST with Smoother,” in Proc. VLSI/CAD Symp., Aug. 2004.

N.-C. Lai and S.-J. Wang, “Low Power BIST with Smoother,” in Proc. 13th Asian Test Symposium, pp. 40-45, Kenting, Taiwan, Nov. 2004.

P.-C. Tsai and S.-J. Wang, “Test Generation and Compaction for Continuous Scan,” in Proc. VLSI/CAD Symp., Aug. 2003.

P.-C. Tsai and S.-J. Wang, “Test Pattern Reordering for Low-Power Testing,” in Proc. VLSI/CAD Symp., Aug. 2002.

C.-F. Huang and S.-J. Wang, “Design of Low-Cost Self-Checking Circuits,” in Proc. Int’l Computer Symp., Dec. 2002.

N.-C. Lai and S.-J. Wang, “A Reseeding Technique for LFSR-Based BIST Applications,” in Proc. 11th Asian Test Symposium, pp. 200-204, Nov. 2002.

Y.-L. Hsu and S.-J. Wang, “Retiming-based logic synthesis for low-power,” in Proc. Int’l Symp. Low Power Electronics and Devices (ISLPED), pp. 275-278, Montery, CA USA., 2002.

S.-J. Wang and Y.-H. Lin, “An adjustable BIST TPG design for low-power testing,” in Proc. 12th VLSI/CAD Symp., 2001.

P.-C. Tsai and S.-J. Wang, “An FSM-based programmable memory BIST architecture,” in Proc. 2nd Workshop on Register Transfer Level Automatic Test Pattern Generation & Design for Testability (WRTL’01), pp. 97-104, Nara, Japan, Nov. 2001.

S.-J. Wang and S.-N. Chiou, “Generating efficient tests for continuous scan,” in Proc. Design Automation Conf., pp. 162-165, Las Vegas, Nevada, USA, June 2001.

S.-J. Wang and C.-J. Wei, “Efficient built-in self-test algorithm for memory,” in Proc. Asian Test Symposium, Taipei, Taiwan, Dec. 2000.

S.-J. Wang, “Bus interface design for high performance computer systems,” 微處理機研討會論文集, pp. 61-66, Hsinchu, Taiwan, May 1999.

W. Lin and S.-J. Wang, “NSC98 Bus Interface Unit,” 微處理機研討會論文集, pp. 55-60, Hsinchu, Taiwan, May 1999.

C.-Z. Yung and S.-J. Wang, “Behavioral synthesis-for-testability for conditional statements with multiple branches,” in Proc. Workshop on Computer Architecture, ICS’98, pp. 15-21, Tainan, Taiwan, Dec. 1998.

S.-J. Wang and C.-N. Huang, “Testing and diagnosis of interconnect structures in FPGAs,” in Proc. 7th Asian Test Symposium, pp 283-287, Singapore, Nov. 1998.

S.-J. Wang, J.-F. Yu, and C.-H. Ko, “Testing interconnect faults in core-based systems,” in Proc. 8th VLSI/CAD Symp., pp.47-50, Nanto, Taiwan, 1997.

S.-J. Wang, “Adaptive system-level diagnosis and its application,” in Proc. 1997 Pacific Rim Intl. Symp. on Fault-Tolerant Systems, pp. 66-71. Taipei, Taiwan, Dec. 1997.

S.-J. Wang and T.-M. Tsai, “Tset and diagnosis of faulty logic blocks in FPGAs,” in Proc. Int’l Conf. on Computer-Aided Design, pp.722-727, San Jose, CA, USA, 1997.

S.-J. Wang, “Generating compact test set for sequential circuits using finite state machine model,” in Proc. 7th VLSI Design/CAD Symp., pp.57-60, 1996.

S.-J. Wang and M.-D. Horng, “State assignment for lower power consumption in sequential circuitst,” in Proc. Int’l Conf. on Computer Architecture (ICS’96), pp. 210-217, Kaohsiung, Taiwan, 1996.

P.C. Hsu and S.-J. Wang, “Testing and diagnosis of board interconnects in microprocessor-based systems,” in Proc. 5th Asian Test Symp., pp.56-61, Hsinchu, Taiwan, 1996.

C.-C. Wang and S.-J. Wang, “Reducing test cost of sequential machines with lower hardware overhead,” in Proc. Workshop on Computer Applications, pp. 22-27, 1995.

S.-J. Wang, “Load-balancing in multi-stage interconnection networks under multiple-pass routing,” in Proc. Nat’l Computer Symp., pp.302-306, 1995.

S.-J. Wang, “Synthesis of sequential machines with reduced testing cost,” in Proc. European Design and Test Conf., pp.302-306, 1994.

S.-J. Wang, “Load-balancing in multi-stage interconnection networks under multiple-pass routing,” in Proc. Nat’l Computer Symp., pp. 61-68, 1993.

C.-C. Wang and S.-J. Wang, “A new expander design for a wideband switching system,” in Proc. Workshop on Computer Applications, pp. 154-159, 1993.

S.-J. Wang, “Distributed diagnosis of faults in multi-stage interconnection networks,” in Proc. Int’l Conf. on Parallel and Distributed Systems, pp. 477-481, 1993.

S.-J. Wang and V. P. Kumar, “Distributed routing in a fault-tolerant multistage interconnection network,” in Proc. Int’l Computer Symp., pp. 838-845, 1992.

N. K. Jha, S.-J. Wang and P. C. Gripka, “Multiple input bridging fault detection in CMOS sequential circuits,” in Proc. IEEE Int. Conf. Computer Design, pp. 369-372, 1992.

S.-J. Wang and N. K. Jha, “Algorithm-based fault-tolerance for FFT networks,” in Proc. Int’l Symp. Circuits and Systems, pp. 141-144, 1992.

N. K. Jha and S.-J. Wang, “Design and synthesis of self-checking VLSI circuits and systems,” in Proc. IEEE Int’l Conf. on Computer Design, pp. 578-581, 1991.

S.-J. Wang and V. P. Kumar, “Distributed diagnosis of faults in a multi-path multistage interconnection network,” in Proc. European Test Conf., pp. 133-141, 1991.

V. P. Kumar and S.-J. Wang, “Dynamic full access in fault-tolerant multistage interconnection networks,” in Proc. Internal Conf. on Parallel Processing, pp. 621-630, 1990.

其它出版品

S.-J. Wang and N. K. Jha, ” Algorithm-based fault-tolerance for FFT networks, ” Technical Report, CE-J92-001,Department of Electrical Engineering, Princeton University, Princeton, NJ 08544, U.S.A.

S.-J. Wang, ” Design and analysis of fault-tolerant multistage interconnection networks, ” Ph.D. Dissertation, Dept. of Electrical Engineering, Princeton University, Jul. 1992.

S.-J. Wang , ” 內嵌於系統級封裝之被動元件測試裝置” 經濟部智慧財產局專利核准號:098139080,Feb 2014

學院簡介

電資學院副院長

王行健(Sying-Jyan Wang)

重要經歷

Vice Dean, College of Electrical Engineering and Computer Science, National Chung Hsing University

Professor, Institute of Computer Science, National Chung Hsing University

Associate Professor, National Chung-Hsing University

Consultant, Bell Laboratories (Holmdel, NJ)

著作目錄

期刊論文

研討會論文

其它出版品